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Data channels


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(5 pages)
 
AZCONDCORR CMER COND_DLG2_F3_VDC
AZCONDCORREQ CMHR COND_DLG3_F0
AZCONDEQ CMLL COND_DLG3_F0_SIG
BACKGROUND_CONDUCTIVITY CMLR COND_DLG3_F0_VDC
CATR CMLX COND_DLG3_F1
CATR_RT CMRM COND_DLG3_F1_SIG
CB1 CMSF COND_DLG3_F1_VDC
CB1A CMSX COND_DLG3_F2
CB2 CMVB COND_DLG3_F2_SIG
CB2A CMVR COND_DLG3_F2_VDC
CB3 COND_BD COND_DLG3_F3
CB3A COND_BD_RT COND_DLG3_F3_SIG
CB4 COND_BD_T1 COND_DLG3_F3_VDC
CB4A COND_BD_T2 COND_DLG4_F0
CC01 COND_BIT COND_DLG4_F0_SIG
CC02 COND_BIT_OBM COND_DLG4_F0_VDC
CC03 COND_BIT_RT COND_DLG4_F1
CC04 COND_BM COND_DLG4_F1_SIG
CC05 COND_BM_RT COND_DLG4_F1_VDC
CC06 COND_BM_T1 COND_DLG4_F2
CC07 COND_BM_T2 COND_DLG4_F2_SIG
CC08 COND_BS COND_DLG4_F2_VDC
CC09 COND_BS_RT COND_DLG4_F3
CC10 COND_BS_T1 COND_DLG4_F3_SIG
CC11 COND_BS_T2 COND_DLG4_F3_VDC
CC12 COND_BX COND_DTE1_F0
CDBC COND_BX_RT COND_DTE1_F0_SIG
CDCR COND_DLG1_F0 COND_DTE1_F0_VDC
CDCX COND_DLG1_F0_SIG COND_DTE1_F1
CDEB COND_DLG1_F0_VDC COND_DTE1_F1_SIG
CDER COND_DLG1_F1 COND_DTE1_F1_VDC
CDHR COND_DLG1_F1_SIG COND_DTE1_F2
CDLR COND_DLG1_F1_VDC COND_DTE1_F2_SIG
CDLX COND_DLG1_F2 COND_DTE1_F2_VDC
CDRM COND_DLG1_F2_SIG COND_DTE1_F3
CDVB COND_DLG1_F2_VDC COND_DTE1_F3_SIG
CDVR COND_DLG1_F3 COND_DTE1_F3_VDC
CIDP COND_DLG1_F3_SIG COND_DTR1_F0
CILD COND_DLG1_F3_VDC COND_DTR1_F0_SIG
CILM COND_DLG2_F0 COND_DTR1_F0_VDC
CIMP COND_DLG2_F0_SIG COND_DTR1_F1
CIRD COND_DLG2_F0_VDC COND_DTR1_F1_SIG
CIRM COND_DLG2_F1 COND_DTR1_F1_VDC
CIXD COND_DLG2_F1_SIG COND_DTR1_F2
CIXM COND_DLG2_F1_VDC COND_DTR1_F2_SIG
CLL8 COND_DLG2_F2 COND_DTR1_F2_VDC
CLLD COND_DLG2_F2_SIG COND_DTR1_F3
CMBC COND_DLG2_F2_VDC COND_DTR1_F3_SIG
CMCR COND_DLG2_F3 COND_DTR1_F3_VDC
CMCX COND_DLG2_F3_SIG COND_DTR2_F0
CMEB
 
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